Hardware Realization of a MASH-111 Delta-Sigma Modulator

High-speed digital Delta-Sigma modulator design in TSMC 16nm FinFET technology.

Overview

Designed and synthesized a high-speed MASH-1-1-1 Digital Delta-Sigma Modulator targeting a 500MHz clock frequency using the TSMC 16nm FinFET technology library. The project involved complete RTL design, multi-corner synthesis using Synopsys Design Compiler, and sign-off quality power/timing analysis using PrimeTime PX.

Project Files
Verilog & TCL Scripts

Project Architecture

Top-Level Block Diagram of the MASH-1-1-1 Modulator, showing the three cascaded accumulator stages, pipelined delay alignment, and the digital noise cancellation logic.

Performance Metrics

Metric Value
Technology TSMC 16nm CMOS
Clock Frequency 500 MHz (Period: 2.0 ns)
Total Power (Sign-off) 0.178 mW (PrimeTime PX / TT Corner)
Total Area 176.62 μm2
Setup / Hold Slack 1.16 ns / 0.00 ns (MET)
Final performance summary verified under multi-corner conditions (SS 125°C for Setup, FF -40°C for Hold).

Technical Details

  • MASH-1-1-1 Architecture Implementation:
    • Cascaded three 1st-order accumulators to effectively randomize quantization noise.
    • Implemented unconditional stability logic superior to single-loop higher-order structures.
  • Advanced Noise Shaping Logic:
    • Designed a cascaded differentiation network $(1-z^{-1})^3$ to push quantization noise to high frequencies.
    • Handled 1-bit carry signals using 5-bit signed arithmetic with bit-extension to accommodate the dynamic range of -3 to +4.
  • High-Speed Pipelining & Timing Closure:
    • Integrated $z^{-1}$ and $z^{-2}$ registers for critical path alignment.
    • Achieved timing closure at 500MHz by resolving setup violations in the Slow-Slow (SS) corner.
    • Addressed hold time violations in the Fast-Fast (FF) corner by inserting 94 buffer/inverter cells automatically via TCL constraints.

Key Features

  • Sign-off Quality Verification: Power analysis performed using PrimeTime PX with vector-based VCD files from gate-level simulation.
  • Multi-Corner Robustness: Validated against extreme process variations (Temp: -40°C to 125°C).
  • Automated Synthesis Flow: Developed TCL scripts for Design Compiler to automate compilation, area optimization, and hold-time fixing.
  • Precision Arithmetic: Bit-true implementation ensuring no overflow in the noise cancellation network.

Technical Stack

  • Languages: Verilog HDL, TCL Scripting
  • EDA Tools: Synopsys Design Compiler, Synopsys PrimeTime PX, Mentor Graphics ModelSim
  • Process Technology: TSMC 16nm FinFET
  • Methodology: Logic Synthesis, Static Timing Analysis (STA), Gate-Level Simulation

Course

UCLA ECE M216A – Design of VLSI Circuits and Systems (25Fall) – Hooman Darabi