5 Gb/s Wireline Transmitter with Low-Jitter PLL

High-speed transmitter in 180nm CMOS featuring a 2.5 GHz LC-VCO and hybrid divider architecture.

Overview

Designed and optimized a complete 5 Gb/s Non-Return-to-Zero (NRZ) wireline transmitter using 180nm CMOS technology. The architecture integrates a high-performance Type-II, 3rd-order PLL providing a stable 2.5 GHz clock, an 8-to-1 serializer MUX tree, and a differential line driver. Key design focuses included flicker noise mitigation in the LC-VCO, current matching in the charge pump, and achieving high energy efficiency of 5.942 pJ/bit.

Project Documents
Final Project Report

Project Architecture

Complete schematic of PLL, featuring a fully integrated Type-II PLL (PFD, Charge Pump, 3rd-order Loop Filter, and LC-VCO) with a hybrid divider chain.

Performance Metrics

Metric Value Specification
Technology 180nm CMOS Standard Process
Data Rate 5 Gb/s (NRZ) ≥ 5 Gb/s
Total Power 29.71 mW Measured
Energy Efficiency 5.942 pJ/bit Competitive
RMS Jitter < 4 ps ≤ 4 ps
Reference Spur -56.82 dBc ≤ -30 dBc
Phase Noise -131.39 dBc/Hz @ 10 MHz offset

Technical Details

  • Low-Noise LC-VCO Design:
    • Implemented a cross-coupled NMOS topology with a 120 µm width to specifically suppress 86% flicker noise ($1/f$) contribution.
    • Optimized the LC tank with $L = 1$ nH ($Q=8$) and a combination of NMOS varactors and fixed capacitors to achieve a robust 2.5 GHz oscillation with precise tuning.
  • Hybrid Divider & Level Shifter:
    • Utilized a high-speed CML divide-by-2 stage for the 2.5 GHz VCO output and a $C^2$MOS stage for power-efficient intermediate division.
    • A self-biased inverter with AC-coupling (200 fF) restores low-swing CML signals to rail-to-rail CMOS levels.
  • Current-Steering Charge Pump & LPF:
    • Designed a current-steering CP with matched current mirrors to minimize charge injection and $V_{cont}$ ripple.
    • Integrated a 3rd-order Loop Filter ($R_0 = 5$ kΩ, $C_1 = 12.7$ pF, $C_0 = 1.3$ pF) for stability and spur attenuation.
  • Serializer & Differential Driver:
    • Implemented an 8-to-1 serializer tree using $C^2$MOS logic and retiming latches to ensure timing margin at 5 Gb/s.
    • Optimized the driver for an on-resistance of 55–58 Ω to maintain a 1.06 V differential output swing across a 50 Ω load.

Simulation Results

PLL Transient Analysis. Left: Synchronized multi-phase clocks (2.5/1.25/0.625 GHz). Right: Control voltage ($V_{cont}$) settling between 885 mV and 929 mV.
Final 5 Gb/s differential output eye diagram, demonstrating a clear 0.9 UI opening and 1.06 V peak-to-peak differential swing.

Technical Stack

  • EDA Tools: Cadence Virtuoso, Spectre Simulator, ADE Explorer/Assembler
  • Design Modules: LC-VCO, PFD/CP, LPF, CML/C2MOS Dividers, 8:1 Serializer, Line Driver
  • Methodology: Frequency Synthesizer Design, Noise/Spur Optimization, High-Speed Link Budgeting

Course

UCLA ECE 215E – Mixed-Signal IC Design (26Winter) – Prof. Behzad Razavi