High-Precision Fully-Differential Folded-Cascode Op-Amp

Low-power analog amplifier design in 180nm CMOS with continuous-time CMFB.

Overview

Designed and optimized a fully-differential Folded-Cascode Operational Amplifier using 180nm CMOS technology. The project focused on the trade-off between power consumption and settling speed, culminating in a low-power design (2.21 mW) that drives a 2 pF capacitive load with <1% gain error and a 1.6 $V_{pp}$ output swing. The design features a robust triode-region Common-Mode Feedback (CMFB) network and systematic mismatch mitigation techniques.

Project Documents
Final Design Report

Project Architecture

Schematic of the Low-Power (Version 2) Fully-Differential Folded-Cascode Amplifier, featuring NMOS input pairs and a passive triode-region CMFB network.

Performance Metrics

Metric Value (Low-Power Ver.)
Technology 180nm CMOS
Supply Voltage 1.8 V
Total Power 2.21 mW
Output Swing 1.6 Vpp (Differential)
Settling Time (99%) 45 ns
Gain Error < 1% (Closed-Loop Gain = 8)
Load Capacitance 2 pF
Performance summary for the optimized low-power design variant, satisfying all settling and accuracy requirements.

Technical Details

  • Folded-Cascode Topology:
Figure 1: NMOS-input Folded-Cascode architecture selected for high-speed operation.
  • Selected an NMOS-input folded-cascode architecture to maximize transconductance ($g_m$) and Gain-Bandwidth Product (GBW) for high-speed operation.

  • Allocated overdrive voltages ($V_{ov}$) meticulously to ensure all transistors remain in saturation while supporting a wide 1.6 $V_{pp}$ output swing.

  • Triode-Region CMFB:
Figure 2: Continuous-time CMFB utilizing triode-region transistors for zero static power.
  • Implemented a continuous-time Common-Mode Feedback network using transistors in the triode region.

  • Advantage: Eliminates the need for resistive dividers (saving area) and avoids consuming voltage headroom at the output nodes.

  • Settling Time Optimization:
    • Identified a critical bottleneck where large CMFB devices introduced excessive parasitic capacitance at the output nodes.
    • Optimization: Reduced CMFB device sizes by 50%, significantly lowering capacitive loading and improving the slewing / small-signal settling time without compromising stability.
  • Systematic Mismatch Mitigation:
    • Inserted compensation resistors in the bias branches to equalize $V_{DS}$ between the current mirror reference and the main tail current source.
    • This ensures precise current mirroring ratios and robust DC operating points by mitigating Channel Length Modulation (CLM) effects

Simulation Results

Transient response to a 100 mV differential step input. The output settles to within 1% accuracy in approximately 45 ns.

Technical Stack

  • EDA Tools: Cadence Virtuoso Schematic Editor, Spectre Simulator, Virtuoso ADE
  • Process Technology: 180nm CMOS
  • Methodology: Analog Circuit Design, Sizing & Biasing, Parasitic Estimation, Transient/AC Analysis

Course

UCLA EE 215A – Analog Integrated Circuit Design (25Fall) – Prof. Behzad Razavi